Description
This Course is of VLSI Programming from Basic (logic gate design) to Advance Design (Structural Design and State Machine Design). After completing the course student will get idea of VLSI programming design methodology, VIVADO Design Flow, Zynq Architecture, Creating Simulation Testbench, Conditional Statements, Combinational Circuit Design with VHDl, Sequential Circuit Design, Structural Design in VHDL and State Machine Design in VHDL. In each section we have included Lab session on VIVADO which have been implemented on Zynq Board (i.e ZedBoard) FPGA, so Student will get complete design skill on VHDL with VIVADO.
Learning Outcomes
- Idea of VHDL Programming , VIVADO Design Methodology and Designing/Implementing Design in Zynq FPGA-ZedBoard
- Use fundamental VHDL constructs to create simple designs. Understanding the Conditional Statements in VHDL.
- Design Simulation testbench on VHDL and simulating the designs.
- Design with structural design methodology on VHDL.
- Designing Decoder, Adder, Register and Counter in VHDL and Implementing in ZedBoard
- Implementing State Machine in VHDL; Designing/Implementing Sequence Detector
Requirements
- Basic idea of VHDL
- Idea of VIVADO Design Suit and Zynq 7000 Architecture
- FPGA Design Methodology Basic
- We have included all the basics of VHDL, VIVADO and Zynq in this Course, So No Worries!!!
Target Audience-
- Electronics Engineering
- Computer Science
- Electrical Engineering
- Robotics Enthusiast
- Embedded System
Course Features
- Lectures 0
- Quizzes 0
- Duration 30 min for each class
- Skill level All levels
- Language English
- Students 138
- Assessments Yes